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Guild: wafer.space Community
Channel: 📐 - Designing / 📝-project-template / This impacts us and while we have
After: 2026-06-30 11:59 p.m.
Before: 2026-08-01 12:00 a.m.
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[2026-07-14 6:50 p.m.] mole99



[2026-07-14 6:50 p.m.] mole99
That is really unfortunate. However, the 3.3V SCL was noted as experimental.

You can create a post under #⁉️-questions with your issue, and I or others might be able to help.

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[2026-07-14 9:53 p.m.] tholin
Have you tried increasing the timing repair margins:
```
PL_RESIZER_SETUP_SLACK_MARGIN: 0.1
GRT_RESIZER_SETUP_SLACK_MARGIN: 0.1
GRT_RESIZER_HOLD_SLACK_MARGIN: 0.15
PL_RESIZER_HOLD_SLACK_MARGIN: 0.15
```


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